World's smallest ultra-compact package
Wafer-level CSP is the world's smallest ultra-small package that supports high performance and miniaturization represented by mobile devices.
LAPIS Technology develops based on the packaging technology cultivated for its own semiconductor devices, develops the latest package foundry services, and strongly supports customers' excellent product development.
Ultra-small and lightweight! 10% of mounting area and 10% of weight * 1 Revolutionary small package* 1: Compared with conventional 100-pin TQFP
256 0.5 0.26 5
25 0.5 0.03
Realized 0.3mm typ. Thickness
Since the device surface is sealed with resin, it can be mounted with a batch reflow device like a conventional package.
Excellent reflow resistance (JEDEC level 1) achieved by material / process technology.
Excellent electrical characteristics can be realized by controlling wiring width, wiring length, multilayer wiring, etc.
(Microcontroller, power supply IC, ASIC, sound source IC, RFIC, memory such as EEPROM, etc.)
Reference reliability evaluation results
|High temperature operation test (Ta : 125°C、VDD : 3.6V)||1000H Pass|
|High temperature storage test (Ta : 150°C)||1000H Pass|
|High temperature and high humidity bias test (Ta : 85°C、RH : 85%、VDD : 3.6V)||1000H Pass|
|Japanese steam unsaturated pressurization test (Ta : 121°C、RH : 85%)||300H Pass|
|Temperature cycle test (-65°C to RT to 150°C)||500cyc. Pass|
|Wafer diameter||6 inches, 8 inches|
|Terminal material||Eutectic, Pb-free（Sn-Ag-Cu）|
To promote customer development and achieve mass production goals
- Our quick response by direct access to key persons for each item
- Thermal resistance analysis, electrical characteristics analysis support
We will support you strongly.